This invention relates to a self-diagnosable integrated circuit device which is capable of diagnosing an internal logic circuit included in the self-diagnosable integrated circuit device.
In general, an integrated circuit device comprises a plurality of circuit elements which are classified into combinational circuit elements, such as AND gates and/or OR gates and sequential circuit elements, such as flip-flops, registers, and/or memories. The integrated circuit device carries out desired processing operations on an input data signal by the use of such circuit elements. It is a recent trend that the circuit elements included in the integrated circuit device remarkably increase in number with development of an integrated circuit technique. Under the circumstances, it becomes necessary to faithfully assure a quality of the integrated circuit device and to locate a fault when the integrated circuit device is faulty. For this purpose, a test must be made to diagnose the integrated circuit device on designing and manufacturing the same. Such a test is also often made when such an integrated circuit device is used in customers.
In Unexamined Japanese Patent Publication No. Syo 60-68,624, namely, 68,624/1985, a self-diagnosable integrated circuit device is proposed by S. Seibu and comprises an internal logic circuit operable as a gate array or the like and a test circuit united with the internal logic circuit to diagnose the internal logic circuit. With this structure, it is readily possible to test and evaluate the internal logic circuit by the use of the test circuit.
More particularly, the self-diagnosable integrated circuit device is operable in a normal mode and a test mode. In the normal mode, the internal logic circuit carries out processing operations on an input data signal in accordance with control signals.
In the test mode, an internal test pattern signal is processed in lieu of the input data signal in response to an internal timing signal determined for each control signal. Thus, external signals, such as the input data signal and the control signal, are not given from an external circuit to the self-diagnosable integrated circuit device in the test mode. At any rate, each processing operation can be carried out inside the self-diagnosable integrated circuit by the use of the internal test pattern signal and the internal timing signal. As a result, it is possible to diagnose and evaluate the internal logic circuit at every processing operation and to locate a fault in the internal logic circuit with a high reliability.
However, no consideration is directed to a self-diagnosable integrated circuit device including complicated sequential circuit elements. This means that a complete test can not be expected when such complicated sequential circuit elements are included in the self-diagnosable integrated circuit device. More specifically, it is assumed that the internal logic circuit comprises, as the sequential circuit elements, an internal memory for storing data signals and that a certain processing operation is carried out by the use of both the stored data signal or signals and a following data signal. Let such a self-diagnosable integrated circuit device be tested by the use of the internal test pattern signal and the internal timing signal in the above-mentioned manner. In this event, no stored data signal is definite in the internal memory when the internal test pattern signal and the internal timing signal are generated in the test circuit of the self-diagnosable integrated circuit device. Therefore, it is difficult to completely predict and estimate an output data signal which is to be produced from the self-diagnosable integrated circuit device in response to the internal test pattern signal and the internal timing signal.
On the other hand, it is possible to diagnose sequential circuit elements by handling the sequential circuit elements as a shift register string in a known manner. However, such sequential circuit elements are never tested in relation to a control signal determined for processing operations of an internal logic circuit.